Interposer and semiconductor device

ABSTRACT

An interposer and a semiconductor device including the interposer are provided, which can prevent thermal warpage of an insulative substrate thereof. The interposer is provided with a semiconductor chip in a semiconductor device andmay be disposed between the semiconductor chip and a mount board. The interposer includes: a substrate of an insulative resin; an island on one surface of the substrate to be bonded to a rear surface of the chip; a thermal pad on the other surface opposite the one surface opposed to the island with the intervention of the substrate; and a thermal via extending through the substrate from the one surface to the other surface to thermally connect the island to the thermal pad.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 11/921,573,filed on Dec. 5, 2007, and allowed on Dec. 13, 2010. Furthermore, thisapplication claims the benefit of priority of Japanese applications2005-165801, filed Jun. 6, 2005 and 2005-240286, filed Aug. 22, 2005.The disclosures of these prior U.S. and Japanese applications areincorporated herein by reference.

TECHNICAL FIELD

The present invention relates to an interposer and a semiconductordevice including the interposer.

BACKGROUND ART

In recent years, surface-mountable packages which permit surfacemounting of semiconductor devices on a wiring board are frequentlyemployed for higher density integration of the semiconductor devices onthe wiring board. BGA (Ball Grid Array) packages are known as typicalexamples of such surface-mountable packages.

A semiconductor device employing a BGA package includes a semiconductorchip mounted on an interposer. The interposer includes an insulativesubstrate of a glass epoxy resin. Provided on one surface of theinsulative substrate are an island on which the semiconductor chip isbonded, and internal terminals respectively electrically connected topads on a front surface of the semiconductor chip via bonding wires.Provided on the other surface of the insulative substrate areball-shaped external terminals for electrical connection to lands(electrodes) provided on a mount board (printed wiring board). Theinsulative substrate has through-holes extending therethrough from theone surface to the other surface thereof. The through-holes are filledwith a metal material. The internal terminals on the one surface of theinsulative substrate are respectively electrically connected to theexternal terminals on the other surface via metal portions provided inthe through-holes.

Patent Document 1: Japanese Unexamined Patent Publication No.2001-181563 DISCLOSURE OF THE INVENTION Problems to be Solved by theInvention

However, the one surface and the other surface of the insulativesubstrate are different in structure. Therefore, when an ambienttemperature around the semiconductor device significantly changes, theinsulative substrate is liable to suffer from a thermal expansiondifference between the one surface and the other surface thereof, andwarp (thermally warp) due to the thermal expansion difference.

Where the semiconductor chip is formed with a power IC, for example, thesemiconductor chip is operative with its rear surface (a rear surface ofa semiconductor substrate thereof) grounded. If the BGA package isemployed for the semiconductor device including the semiconductor chipformed with the power IC, it is necessary to electrically connect theisland to the external terminals and to bond the rear surface of thesemiconductor chip to the island with the use of a bonding agent havingelectrical conductivity (an electrically conductive bonding agent). Forthe semiconductor device employing the BGA package, however, it is acommon practice to employ an insulative bonding agent such as an epoxyresin adhesive or an insulative paste as the bonding agent for bondingthe semiconductor chip to the island, but an electrically conductivebonding agent such as a solder bonding agent is not hitherto employed.Where the solder bonding agent is employed, a reflow process isindispensable. When the interposer mounted with the semiconductor chipis heated at a high temperature (e.g., about 260° C.) in the reflowprocess, the insulative substrate is warped due to a difference inthermal expansion degree between the one surface and the other surfaceof the insulative substrate.

In a semiconductor device employing a BGA package or an LGA (Land GridArray) package, a semiconductor chip is bonded to an insulativesubstrate of a resin or a ceramic material having a lower thermalconductivity and, therefore, heat generated by the semiconductor chipcannot be sufficiently dissipated as compared with a semiconductordevice of a QFP (Quad Flat Package) employing a lead frame havingexcellent thermal conductivity. This makes it difficult to keep thetemperature of the semiconductor chip at a level not higher than apermissible temperature. In recent years, higher functionalities ofsemiconductor chips tend to increase the amounts of heat generated bythe semiconductor chips. Accordingly, there is a demand for asemiconductor device having an excellent heat dissipating capability.

For example, Patent Document 2 proposes a semiconductor device whichincludes pads respectively connected to electrodes provided on an uppersurface of a semiconductor chip via wires, and a heat-sink electrode(metal plate) on which the semiconductor chip is bonded via a bondingmaterial, and is substantially entirely sealed with a resin with thepads and the heat-sink electrode partly uncovered. In the semiconductordevice, heat generated by the semiconductor chip is dissipated throughthe heat-sink electrode.

However, the construction of the semiconductor device requireselectrical insulation between the heat-sink electrode and the pads, sothat an insulative adhesive or an insulative sheet having lower thermalconductivity should be employed as the bonding agent. Therefore, theheat is less liable to be transferred from the semiconductor chip to theheat-sink electrode, so that the heat generated by the semiconductorchip cannot be sufficiently dissipated.

Further, Patent Document 3 proposes a semiconductor device whichincludes a semiconductor chip of a lower surface electrode (face down)type having a multiplicity of connection electrodes provided on a lowersurface (mount surface) thereof, a periphery reinforcement dummyelectrode provided on a peripheral portion of the lower surface thereofand a center reinforcement dummy electrode provided on a center portionof the lower surface thereof, and an insulative substrate havingconnection lands provided on a front surface thereof and respectivelyconnected to the connection electrodes, a periphery reinforcement landprovided on the front surface thereof and connected to the peripheryreinforcement dummy electrode and a center reinforcement land providedon the front surface thereof and connected to the center reinforcementdummy electrode. A heat-sink conductor layer is provided on a rearsurface of the insulative substrate, and is connected to the centerreinforcement land via a heat-sink via extending through the insulativesubstrate. In the semiconductor device, heat generated by thesemiconductor chip can be dissipated through a heat conduction pathincluding the center reinforcement dummy electrode, the centerreinforcement land, the heat-sink via and the heat-sink conductor layerwhich are highly thermally conductive.

Of the electrodes provided on the semiconductor chip, however, only thecenter reinforcement dummy electrode is connected to the heat-sinkconductor layer in the semiconductor device. With a smaller number ofheat conduction paths, the semiconductor device is problematic in thatthe heat generated by the semiconductor chip cannot be sufficientlydissipated. Further, the center reinforcement dummy electrode is locatedat the center of the lower surface of the semiconductor chip, making itdifficult to dissipate the heat from the entire semiconductor chip.Furthermore, the semiconductor chip is of the lower surface electrode(face down) type. Therefore, it is difficult to provide a sufficientnumber of center reinforcement dummy electrodes for the heat dissipationon the lower surface of the semiconductor chip.

It is a first object of the present invention to provide an interposerand a semiconductor device including the interposer, which can preventthermal warpage of an insulative substrate thereof.

It is a second object of the present invention to provide asemiconductor device having an excellent heat dissipating capability andto provide an interposer to be employed for the semiconductor device.

Means for Solving the Problems

An interposer according to one aspect of the present invention toachieve the aforementioned first object is an interposer which is to beprovided together with a semiconductor chip in a semiconductor deviceand, when the semiconductor device is mounted on a mount board, disposedbetween the semiconductor chip and the mount board. The interposerincludes: an insulative substrate of an insulative resin; an islandprovided on one surface of the insulative substrate to be bonded to arear surface of the semiconductor chip via a bonding agent; a thermalpad provided on the other surface of the insulative substrate oppositefrom the one surface in generally opposed relation to the island withthe intervention of the insulative substrate; and a thermal viaextending through the insulative substrate from the one surface to theother surface to connect the island to the thermal pad in a thermallyconductive manner.

A semiconductor device according to another aspect of the presentinvention to achieve the aforementioned first object includes: asemiconductor chip; an insulative substrate of an insulative resin; anisland provided on one surface of the insulative substrate and bonded toa rear surface of the semiconductor chip via a bonding agent; a thermalpad provided on the other surface of the insulative substrate oppositefrom the one surface in generally opposed relation to the island withthe intervention of the insulative substrate; and a thermal viaextending through the insulative substrate from the one surface to theother surface to connect the island to the thermal pad in a thermallyconductive manner.

The island is disposed on the one surface of the insulative substrate,while the thermal pad is disposed on the other surface of the insulativesubstrate opposite from the one surface in generally opposed relation tothe island with the intervention of the insulative substrate. The islandand the thermal pad are connected to each other in a thermallyconductive manner by the thermal via extending through the insulativesubstrate. Therefore, even if an ambient temperature around thesemiconductor device abruptly changes, a temperature (thermal) balancecan be maintained between the one surface and the other surface of theinsulative substrate. As a result, the insulative substrate is preventedfrom suffering from a thermal expansion difference between the onesurface and the other surface thereof and, therefore, prevented frombeing thermally warped.

Particularly, the thermal pad is preferably composed of the samematerial and has the same configuration (plan shape and thickness) asthe island. In this case, the temperature balance can be maintainedbetween the one surface and the other surface of the insulationsubstrate against the change in ambient temperature around thesemiconductor device, and the thermal expansion/thermal contraction ofthe island can be balanced with the thermal expansion/thermalcontraction of the thermal pad. This further reliably prevents theinsulative substrate from suffering from the thermal expansiondifference between the one surface and the other surface thereof,thereby effectively preventing the thermal warpage of the insulativesubstrate.

The interposer preferably further includes internal terminals providedon the one surface of the insulative substrate for electrical connectionto the semiconductor chip, external terminals provided on the othersurface of the insulative substrate for electrical connection to landson the mount board, and inter-terminal connection vias extending throughthe insulative substrate from the one surface to the other surface torespectively electrically connect the internal terminals to the externalterminals.

With this arrangement, the internal terminals on the one surface of theinsulative substrate are respectively electrically connected to theexternal terminals on the other surface by the inter-terminal connectionvias. Therefore, the electrical connection between the lands and theinternal terminals and hence the electrical connection between the landsand the semiconductor chip are achieved by electrically connecting theexternal terminals to the lands of the mount board.

The interposer preferably further includes a thermal bump provided onthe thermal pad and adapted to abut against the mount board with thesemiconductor device mounted on the mount board.

With this arrangement, the thermal bump provided on the thermal padabuts against the mount board with the semiconductor device mounted onthe mount board. Therefore, the heat is released from the thermal pad tothe mount board through the thermal bump. As a result, the heatdissipating capability of the semiconductor device is improved.

The island, the thermal pad, the thermal via and the thermal bump arepreferably electrically conductive, and the bonding agent is preferablycomposed of a metal material. The thermal bump is preferably adapted toabut against a ground terminal on the mount board with the semiconductordevice mounted on the mount board.

With this arrangement, when the thermal bump is connected to the groundelectrode on the mount board with the semiconductor device mounted onthe mount board, the ground electrode is electrically connected to therear surface of the semiconductor chip through the thermal bump, thethermal pad, the thermal via and the island, because the island, thethermal pad, the thermal via and the thermal bump are electricallyconductive and the bonding agent is composed of the metal material.Therefore, the rear surface of the semiconductor chip is kept at aground potential with the semiconductor device mounted on the mountboard. Hence, a semiconductor chip such as formed with a power IC andoperative with its rear surface grounded may be employed as thesemiconductor chip. In this case, proper operation of the semiconductorchip (e.g., proper operation of the power IC) is ensured.

The bonding agent is preferably a high melting point solder.

The high melting point solder is herein defined as a solder having amelting point of not lower than 260° C.

With this arrangement, when the rear surface of the semiconductor chipis bonded to the island with the use of the high melting point solder, areflow process is required. However, even if the interposer mounted withthe semiconductor chip is heated at a high temperature on the order ofnot lower than 260° C. in the reflow process, the temperature (thermal)balance can be maintained between the one surface and the other surfaceof the insulative substrate. As a result, it is possible to prevent theinsulative substrate from suffering from the thermal expansiondifference between the one surface and the other surface thereof,thereby preventing the thermal warpage of the insulative substrate.

The thermal vias are preferably arranged at a higher density than theinter-terminal connection vias.

With this arrangement, a broader heat conduction path extending from theisland to the thermal pad can be provided. Therefore, the heat generatedby the semiconductor chip is advantageously transferred to the thermalpad, so that the semiconductor device has an excellent heat dissipatingcapability.

An interposer according to one aspect of the present invention toachieve the aforementioned second object includes: an insulativesubstrate having via-holes arranged in a matrix array with anelectrically conductive island provided on a front surface thereof;wherein the insulative substrate has a heat dissipation via-holeprovided in addition to the via-holes arranged in the matrix array in aregion thereof opposed to the island.

A semiconductor device according to another aspect of the presentinvention to achieve the aforementioned second object includes: aninsulative substrate having via-holes arranged in a matrix array with anelectrically conductive island provided on a front surface thereof; anda semiconductor chip die-bonded to the island via an electricallyconductive layer; wherein the insulative substrate has a heatdissipation via-hole provided in addition to the via-holes arranged inthe matrix array in a region thereof opposed to the island.

The electrically conductive island on which the semiconductor chip isdie-bonded contacts substantially the entire lower surface of thesemiconductor chip via the electrically conductive layer. The via-holesarranged in the matrix array and the heat dissipation via-hole aredisposed below the island. Therefore, the electrically conductive layerand the island each having a higher electrical conductivity, thevia-holes and the heat dissipation via-hole provide a broader heatconduction path for dissipating heat generated by the semiconductorchip. As a result, the semiconductor device has an excellent heatdissipating capability.

The matrix array herein means that the via-holes are located at planelattice points to be aligned in rows and columns. However, the rows andthe columns are not necessarily required to be orthogonally intersecteach other, but may form a predetermined angle (e.g., 60 degrees).

Metal terminals are preferably provided on a rear surface of theinsulative substrate and respectively electrically connected to thevia-holes in the region of the insulative substrate opposed to theisland.

With this arrangement, the highly electrically conductive metalterminals (solder bumps or the like) are respectively electricallyconnected to the via-holes. Therefore, heat transferred from thesemiconductor chip through the heat conduction path can be released tothe outside (a printed wiring board or the like) through the metalterminals, so that the heat dissipating capability can be improved.Further, ground electrodes may be provide on a lower surface (mountsurface) of the semiconductor chip and the metal terminals may beconnected to electrodes of a printed wiring board or the like, wherebythe metal terminals serve as ground electrodes of the semiconductordevice.

The via-holes and/or the heat dissipation via-hole are preferably filledwith a metal filler.

With this arrangement, the heat generated by the semiconductor chip canbe more advantageously dissipated, because the via-holes and/or the heatdissipation via-hole are filled with the highly electrically conductivemetal filler. As a result, the heat dissipating capability can befurther enhanced.

The foregoing and other objects, features and effects of the presentinvention will become more apparent from the following detaileddescription of embodiments with reference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view schematically illustrating the constructionof a semiconductor device according to one embodiment of the presentinvention.

FIG. 2 is a schematic plan view of a surface of the semiconductor deviceof FIG. 1 opposed to a mount board.

FIG. 3 is a plan view schematically illustrating the construction of asemiconductor device according to a second embodiment of the presentinvention.

FIG. 4 is a schematic sectional view (a sectional view taken along aline A-A) of the semiconductor device shown in FIG. 3.

FIG. 5A is a plan view schematically illustrating a portion of aninsulative substrate in an island formation region of a semiconductordevice according to a third embodiment of the present invention.

FIG. 5B is a plan view schematically illustrating a portion of aninsulative substrate in an island formation region of a semiconductordevice according to a fourth embodiment of the present invention.

FIG. 6 is a schematic sectional view of an interposer provided in thesemiconductor device shown in FIG. 4.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will hereinafter be described indetail with reference to the attached drawings.

FIG. 1 is a sectional view schematically illustrating the constructionof a semiconductor device according to one embodiment of the presentinvention. The semiconductor device is a semiconductor device employinga BGA (Ball Grid Array) package, and includes a semiconductor chip 1, aninterposer 2 on which the semiconductor chip 1 is mounted, and a resinseal 3 which seals the semiconductor chip 1 and a surface of theinterposer 2 opposed to the semiconductor chip 1.

A semiconductor substrate (e.g., a silicon substrate) serving as a baseof the semiconductor chip 1 is formed, for example, with a power IC. Anoutermost surface of the semiconductor chip 1 is covered with a surfaceprotective film, and a plurality of pads (not shown) are provided on aperipheral portion of the outermost surface of the semiconductor chip 1as being exposed from the surface protective film.

The interposer 2 includes an insulative substrate 4 of an insulativeresin (e.g., a glass epoxy resin).

An island 5 of a rectangular thin plate shape having substantially thesame size as the semiconductor chip 1 as seen in plan is provided on acenter portion of one surface (upper surface) 4A of the insulativesubstrate 4. A plurality of internal terminals 6 are provided on aperipheral portion of the one surface 4A of the insulative substrate 4as surrounding the island 5. The island 5 and the internal terminals 6are each composed of a metal such as copper and, therefore, areelectrically conductive.

A rear surface of the semiconductor chip 1 is bonded to the island 5 viaa bonding agent 7 of a high melting point solder (a solder having amelting point of not lower than 260° C.). The internal terminals 6 arerespectively connected (wire-bonded) to the pads on the front surface ofthe semiconductor chip 1, for example, via bonding wires 8 of gold thinwires. Thus, the rear surface of the semiconductor chip 1 (the rearsurface of the semiconductor substrate) is electrically connected to theisland 5 via the bonding agent 7, and an internal circuit (not shown) ofthe semiconductor chip 1 is electrically connected to the internalterminals 6 via the bonding wires 8.

On the other hand, a thermal pad 9 having substantially the sameconfiguration (plan shape and thickness) as the island 5 and composed ofthe same metal material as the island 5 is provided on a center portionof the other surface (lower surface) 4B of the insulative substrate 4(in opposed relation to the island 5 with the intervention of theinsulative substrate 4). A plurality of thermal vias 10 extend throughthe insulative substrate 4 between the island 5 and the thermal pad 9 toconnect the island 5 and the thermal pad 9 in a thermally conductivemanner. The thermal vias 10 are formed, for example, by formingvia-holes extending through the insulative substrate 4 and filling thevia-holes with a metal material (e.g., copper). Thus, the island 5 andthe thermal pad 9 are connected to each other via the plurality ofthermal vias 10 in a thermally and electrically conductive manner.

A plurality of external terminals 13 for electrical connection to lands(electrodes) 12 on a mount board (printed wiring board) 11 are providedon a peripheral portion of the other surface 4B of the insulativesubstrate 4 as surrounding the thermal pad 9. The external terminals 13are each formed of a metal material such as a solder as having a ballshape. The external terminals 13 are respectively disposed in opposedrelation to the internal terminals 6 with the intervention of theinsulative substrate 4, and wholly arranged in a rectangular frame-likeconfiguration along the peripheral portion of the other surface 4B ofthe insulative substrate 4 as shown in FIG. 2. The external terminals 13are respectively electrically connected to the internal terminals 6opposed thereto via inter-terminal connection vias 14 each extendingthrough the insulative substrate 4. The inter-terminal connection vias14 are formed, for example, by forming via-holes extending through theinsulative substrate 4 and filling the via-holes with a metal material(e.g., copper).

A plurality of thermal bumps 16 for connection to ground electrodes 15on the mount board 11 are provided on the other surface 4B of theinsulative substrate 4. The thermal bumps 16 are each formed of a metalmaterial such as a solder as having a ball-shape, and disposed on thethermal pad 9.

The other surface 4B of the insulative substrate 4 is covered with asolder resist layer 17. The external terminals 13 and the thermal bumps16 partly project from the solder resist layer 17.

Surface mounting of the semiconductor device on the mount board 11 isachieved by connecting the external terminals 13 to the lands 12 on themount board 11 with the other surface 4B of the insulative substrate 4opposed to the mount board 11. That is, the internal terminals 6 on theone surface 4A of the insulative substrate 4 are respectivelyelectrically connected to the external terminals 13 on the other surface4B via the inter-terminal connection vias 14, so that the electricalconnection between the lands 12 and the internal terminals 6 and hencethe electrical connection between the lands 12 and the semiconductorchip 1 can be achieved.

Further, the thermal bumps 16 are respectively connected to the groundelectrodes 15 on the mount board 11 with the semiconductor devicemounted on the mount board 11, whereby the rear surface of thesemiconductor chip 1 is electrically connected to the ground electrodes15 through the bonding agent 7 of the high melting point solder, theisland 5, the thermal vias 10, the thermal pad 9 and the thermal bumps16. Thus, the rear surface of the semiconductor chip 1 is kept at aground potential, thereby ensuring proper operation of the semiconductorchip 1 (proper operation of the power IC).

Where the rear surface of the semiconductor chip 1 is thus bonded to theisland 5 by the bonding agent 7 of the high melting point solder, theelectrical connection between the rear surface of the semiconductor chip1 and the island 5 is achieved by the electrical conductivity of thebonding agent 7. Where the bonding agent 7 of the high melting pointsolder is used, a reflow process is required for melting the bondingagent 7 after the bonding agent 7 is applied (a high melting pointsolder paste is applied) onto the island 5 and the rear surface of thesemiconductor chip 1 is bonded onto the island 5. In the reflow process,the semiconductor chip 1 and the interposer 2 are heated at a hightemperature on the order of not lower than 260° C. At this time, theinsulative substrate 4 is liable to be thermally warped, if atemperature imbalance occurs between the one surface 4A and the othersurface 4B of the insulative substrate 4 and hence a thermal expansiondifference occurs between the one surface 4A and the other surface 4B ofthe insulative substrate 4.

To cope with this, the thermal pad is provided on the other surface 4Bof the insulative substrate 4 in opposed relation to the island with theintervention of the insulative substrate, and the island 5 and thethermal pad 9 are connected to each other in a thermally conductivemanner by the thermal vias 10 extending through the insulative substrate4. Therefore, even if an ambient temperature around the semiconductordevice is abruptly changed in the reflow process, a temperature(thermal) balance can be maintained between the one surface 4A and theother surface 4B of the insulative substrate 4. As a result, it ispossible to prevent the insulative substrate 4 from suffering from thethermal expansion difference between the one surface 4A and the othersurface 4B thereof, thereby preventing the thermal warpage of theinsulative substrate 4.

Further, the thermal pad 9 is composed of the same metal material as theisland 5, and has the same shape as the island 5. Therefore, thetemperature balance can be maintained between the one surface 4A and theother surface 4B of the insulative substrate 4 against the change inambient temperature around the semiconductor device, and the thermalexpansion/thermal contraction of the island 5 can be balanced with thethermal expansion/thermal contraction of the thermal pad 9. This morereliably prevents the thermal expansion difference between the onesurface 4A and the other surface 4B of the insulative substrate 4,thereby effectively preventing the thermal warpage of the insulativesubstrate 4.

In addition, the thermal bumps 16 provided on the thermal pad 9 arerespectively connected to the ground electrodes 15 on the mount board 11with the semiconductor device mounted on the mount board 11, so that theheat is released from the thermal pad 9 to the mount board 11 throughthe thermal bumps 16.

In this embodiment, the island 5 has substantially the same size as thesemiconductor chip 1 as seen in plan, but the size of the island 5 maybe greater or smaller than the size of the semiconductor chip 1 as seenin plan.

Further, the high melting point solder is employed as the bonding agent7 by way of example, but the bonding agent 7 may be, for example, asilver paste which is electrically conductive and capable of bonding(joining) the rear surface of the semiconductor chip 1 to the island 5.

FIG. 3 is a plan view schematically illustrating a semiconductor deviceaccording to a second embodiment of the present invention. FIG. 6 is asectional view (a sectional view taken along a line A-A) of thesemiconductor device shown in FIG. 3.

An insulative substrate 121 provided in a semiconductor device 110 iscomposed of a material obtained by impregnating glass fibers with abismaleimide-triazine resin (BT resin). The insulative substrate 121 isnot particularly limited, as long as it is insulative. Examples of theinsulative substrate include substrates of bismaleimide-triazine resins(BT resins), epoxy resins, polyester resins, polyimide resins and phenolresins, substrates obtained by impregnating reinforcement materials suchas glass fibers with any of these resins, and ceramic substrates.

An island 122 having substantially the same area as a lower surface(mount surface) of a semiconductor chip 111 is provided on a centerportion of a front surface of the insulative substrate 121. The island122 is formed of a Cu layer. An Ni layer and/or an Au layer may beprovided on the Cu layer. The island 122 is not particularly limited, aslong as it is electrically conductive.

A plurality of conductor circuits 123 of Cu layers are provided on aperipheral portion of the front surface of the insulative substrate 121.The conductor circuits 123 each have a pattern such as to extend from aperipheral portion to a center portion of the semiconductor device 110(see FIG. 3). End portions of the respective conductor circuits 123located on the peripheral side are equidistantly arranged alongperipheral edges of the semiconductor device 110, and bonding pads 124are respectively provided on upper surfaces of the end portions. Thebonding pads 124 are each formed of an Ni layer, an Au layer or thelike.

The front surface of the insulative substrate 121 except for the island122 and the bonding pads 124 is covered with a solder resist layer 125.

The semiconductor chip 111 is die-bonded to the island 122 via anelectrically conductive layer 112. Any of various types of semiconductorchips may be employed as the semiconductor chip 111, and the specificfunction and the internal circuit configuration of the semiconductorchip are not particularly limited.

The semiconductor chip 111 has a plurality of electrodes 111 a providedin an upper surface thereof. The electrodes 111 a are respectivelyelectrically connected to the bonding pads 124 via wires 114. In FIG. 3,the electrodes 111 a and the wires 114 are not shown for convenience ofexplanation.

The insulative substrate 121 has 64 via-holes 126 arranged in a matrixarray (8×8) in the entire region thereof including regions inside andoutside an island formation region (which contacts the island 122) (seeFIG. 3). Of the 64 via-holes 126, 4×4 via-holes 126 are located in theisland formation region. The via-holes 126 each have a diameter of about120 to about 150 μm. The via-holes 126 are such that metal thin filmsare provided on sidewalls of through-holes formed in the insulativesubstrate 121 by electroless plating or electrolytic plating and thethrough-holes are filled with a filler.

In addition to the 4×4 via-holes 126, nine heat dissipation via-holes127 are provided in the island formation region of the insulativesubstrate 121 (see FIG. 3). The heat dissipation via-holes 127 are eachequidistantly spaced from four adjacent via-holes 126. The heatdissipation via-holes 127 are such that metal thin films are provided onsidewalls of through-holes formed in the insulative substrate 121 byelectroless plating or electrolytic plating and the through-holes arefilled with a filler. That is, the heat dissipation via-holes 127 eachhave the same shape and structure as the via-holes 126. In FIG. 3 andthe subsequent figures, the heat dissipation via-holes 127 are hatchedfor easy discrimination between the via-holes 126 and the heatdissipation via-holes 127.

The via-holes 126 and the heat dissipation via-holes 127 provided in theisland formation region are electrically connected to the island 122.The via-holes 126 and the heat-dissipation via-holes 127 may be isolatedfrom the island 122, though this embodiment is directed to a case inwhich the via-holes 126 and the heat dissipation via-holes 127 areelectrically connected to the island 122.

A conductor layer 128 having substantially the same area as the island122 is provided on a center portion of a rear surface of the insulativesubstrate 121, and the via-holes 126 and the heat dissipation via-holes127 are electrically connected to the conductor layer 128. Further,conductor layers 128 respectively electrically connected to thevia-holes 126 are provided on a peripheral portion of the rear surfaceof the insulative substrate 121. These conductor layers 128 are eachformed of a Cu layer. The rear surface of the insulative substrate 121is covered with a solder resist layer 130 with the conductor layers 128(associated with the via-holes 126) partly exposed.

Solder pads 29 such as of Ni layers or Au layers are provided on theexposed portions of the conductor layers 128, and solder bumps (metalterminals) 31 are respectively provided on the solder pads 29. Thisembodiment is directed to a case in which the solder bumps 31 arepreliminarily formed on the rear surface of the insulative substrate121, but the semiconductor device may be adapted to be directly mountedon a printed wiring board, for example, with the use of solder balls ora solder paste.

The semiconductor device 110 includes a resin package portion 119 whichseals the semiconductor chip 111 as covering the entire upper surface ofthe insulative substrate 121. The resin package portion 119 is composedof, for example, a resin composition containing an epoxy resin or thelike. In FIG. 3, the resin package portion 119 is not shown.

The island 122 on which the semiconductor chip 111 is die-bondedcontacts substantially the entire lower surface of the semiconductorchip 111 via the electrically conductive layer 112. The via-holes 126arranged in the matrix array and the heat dissipation via-holes 127 aredisposed below the island 122. Therefore, the electrically conductivelayer 112, the island 122, the via-holes 126 and the heat-dissipationvia-holes 127, which are highly electrically conductive, provide abroader heat conduction path for dissipation of heat generated by thesemiconductor chip 111 as shown in FIG. 6. Thus, the semiconductordevice has an excellent heat dissipating capability.

From the viewpoint of the thermal conduction, there is no need todiscriminate the via-holes 126 and the heat dissipation via-holes 127,which may be regarded as thermal vias which connect the island 122 tothe conductor layer 128 as a thermal pad in a thermally conductivemanner.

The solder bumps (metal terminals) 31 respectively electricallyconnected to the via-holes 126 are preferably provided in the islandformation region on the rear surface of the insulative substrate 121.With the highly thermally conductive solder bumps 31 electricallyconnected to the via-holes 126, heat transferred from the semiconductorchip 111 to the via-holes 126 is released to the outside (the printedwiring board or the like) through the solder bumps 31. Therefore, theheat dissipating capability can be further enhanced.

The via-holes 126 and/or the heat dissipation via-holes 127 arepreferably filled with a highly thermally conductive metal filler. Inthis case, the heat generated by the semiconductor chip 111 is moreadvantageously dissipated. As a result, the heat dissipating capabilitycan be further enhanced.

This embodiment is directed to a case in which the heat dissipationvia-holes 127 each have the same diameter as the via-holes 126 and areeach equidistantly spaced from four adjacent via-holes 126. However, theshape and the layout of the heat dissipation via-holes 127 are notparticularly limited. For example, an arrangement as shown in FIG. 5A or5B may be employed.

FIG. 5A is a plan view schematically illustrating a portion of aninsulative substrate in an island formation region of a semiconductordevice according to a third embodiment of the present invention.

In an insulative substrate 132, 16 via-holes 136 are arranged in amatrix array (4×4) in an island formation region. Further, heatdissipation via-holes 137 are arranged between the via-holes 136, i.e.,are each equidistantly spaced from four adjacent via-holes 136. However,the heat dissipation via-holes 137 are greater in diameter than thevia-holes 136.

With the heat dissipation via-holes 137 thus each having a greaterdiameter than the via-holes 136, a broader heat conduction path can beprovided, thereby enhancing the heat dissipating effect. Further, it isdesirable to increase the diameter of each of the heat dissipationvia-holes 137 and reduce the number of the through-holes to provide thesame total opening area while suppressing a cost increase.

FIG. 5B is a plan view schematically illustrating a portion of aninsulative substrate in an island formation region of a semiconductordevice according to a fourth embodiment of the present invention.

In an insulative substrate 142, 16 via-holes 146 are arranged in amatrix array (4×4) in an island formation region. Further, heatdissipation via-holes include first heat dissipation via-holes 147 aeach having a greater diameter than the via-holes 146, and second heatdissipation via-holes 147 b each having a smaller diameter than thevia-holes 146. The first heat dissipation via-holes 147 a are arrangedbetween the via-holes 146, i.e., are each equidistantly spaced from fouradjacent via-holes 146. The second heat dissipation via-holes 147 b areeach disposed between two adjacent via-holes 146.

Thus, the heat dissipation via-holes are not necessarily required tohave the same diameter, but heat dissipation via-holes 147 a, 147 bhaving different diameters may coexist. The provision of the heatdissipation via-holes 147 a, 147 b having different diameters increasesthe total opening area of the heat dissipation via-holes 147 a, 147 b,while ensuring sufficient mechanical strength of the insulativesubstrate 142.

In the present invention, as shown in FIGS. 3, 5A and 5B, the heatdissipation via-holes are desirably disposed between all adjacent pairsof via-holes arranged in the matrix array in the island formationregion. This permits uniform heat dissipation from the entiresemiconductor chip, thereby preventing local temperature increase of thesemiconductor chip.

FIG. 6 is a schematic sectional view of an interposer provided in thesemiconductor device 110 shown in FIG. 4.

The semiconductor device 110 can be produced as having excellent heatdissipating capability by employing the interposer 120.

Next, a method for producing the interposer 120 and a method forproducing the semiconductor device 110 by employing the interposer 120will be described.

(A) An insulative substrate 121 is employed as a starting material.First, an island 122 and conductor circuits 123 are formed on a frontsurface of the insulative substrate 121, and conductor layers 128 areformed on a rear surface of the insulative substrate 121. The formationof the island 122, the conductor circuits 123 and the conductor layers128 is achieved by forming plain metal layers on the opposite surfacesof the insulative substrate 121 by electroless plating or the like, andthen etching the metal layers. Alternatively, the formation may beachieved by etching a copper-coated substrate.

(B) Through-holes (hereinafter referred to as first through-holes) areformed in the insulative substrate 121 as being arranged in a matrixarray by a drill or laser. The first through-holes later serve asvia-holes 126. The first through-holes each have a diameter of, forexample, about 120 to about 150 μm.

Further, through-holes (hereinafter referred to as second through-holes)are formed in an island formation region as being arranged in a matrixarray by a drill or laser. The second through-holes later serve as heatdissipation via-holes 127. The diameter of each of the secondthrough-holes is not particularly limited.

Where the second through-holes each have the same diameter as the firstthrough-holes, the settings of an apparatus employed for the formationof the first through-holes can be employed as they are for the formationof the second through-holes, so that an increase in labor required forthe formation of the through-holes can be suppressed. On the other hand,where the second through-holes are different in diameter from the firstthrough-holes (through-holes having different diameters coexist), it ispossible to form a multiplicity of through-holes while providingsufficient spacings between the through-holes. Therefore, the heatdissipating effect can be enhanced. The second through-holes are notnecessarily required to have the same diameter, but may include pluraltypes of second through-holes having different diameters. Further, it isdesirable to increase the diameter of each of the through-holes andreduce the number of the through-holes to provide the same total openingarea while suppressing a cost increase.

Then, metal thin films are formed on sidewalls of the through-holes (thefirst through-holes and the second through-holes) by performingelectroless plating and then electrolytic plating, and the through-holesare filled with a filler. Thus, the via-holes 126 and the heatdissipation via-holes 127 are formed. The filler is not particularlylimited, but examples thereof include resin fillers and metal fillers.Desirably, the metal fillers are used in order to broaden the heatconduction path for enhancement of the heat dissipating effect. Examplesof the metal fillers include electrically conductive pastes containingmetal particles. The formation of the via-holes 126 and the heatdissipation via-holes 127 may be achieved by filling the through-holesby plating. Alternatively, the via-holes 126 and the heat dissipationvia-holes 127 may be lidded by plating.

(C) Next, an uncured solder resist composition is applied onto the frontsurface of the insulative substrate 121 by means of a roll coater or acurtain coater, or a film of the solder resist composition ispress-bonded onto the front surface, and then the solder resistcomposition is cured. Thus, a solder resist layer 125 is formed.Further, a solder resist layer 130 is formed on the rear surface of theinsulative substrate 121 in the same manner.

In turn, openings are formed at predetermined positions in the solderresist film 125 by a laser process or a photolithography process, andportions of the resulting substrate exposed from the solder resist film125 are plated by Ni plating or Au plating. Thus, the island 122 iscoated with an Ni layer or an Au layer, and bonding pads 124 are formed.Further, solder pads 29 are formed by performing substantially the sameprocess on the solder resist layer 130. Then, solder bumps 31 are formedby applying a solder paste or placing solder balls on the solder pads29, and performing a reflow process.

The interposer 120 is thus produced through the steps (A) to (C) (seeFIG. 6).

(D) Subsequently, a solder paste or an Ag paste is applied onto theisland 122 of the interposer 120, and a semiconductor chip 111 ismounted on the applied solder paste. Then, a reflow process isperformed. Thus, the semiconductor chip 111 is die-bonded to the island122 via an electrically conductive layer 112

Electrodes 111 a provided in an upper surface of the semiconductor chip111 are respectively wire-bonded to the bonding pads 124 with the use ofwires. Then, a resin package portion 119 is formed from a resincomposition containing an epoxy resin or the like as covering the entireupper surface of the insulative substrate 121. Thus, the semiconductordevice 110 is produced.

In the arrangements shown in FIGS. 3 to 6, the via-holes located insidethe island formation region may be different in diameter from thevia-holes located outside the island formation region.

While the embodiments of the present invention have been described, thepresent invention may be embodied in other ways. For example, theinsulative substrate is a single layer substrate in the embodimentsdescribed above, but may be a substrate prepared by stacking a pluralityof plates.

Further, the island has a rectangular shape having substantially thesame size as the lower surface (mount surface) of the semiconductor chipin the embodiments described above, but the shape of the island is notparticularly limited.

The embodiments described above are directed to the semiconductor deviceemploying the BGA, but the present invention may be applied to asemiconductor device employing a so-called LGA (Land Grid Array) inwhich a plurality of lands (external terminals each having a thin plateshape) are arranged on the insulative substrate. Further, the packagetype is not limited to the surface-mountable packages such as BGA andLGA, but the present invention may be applied to a semiconductor deviceemploying an insertion type mount package which achieves the mounting ofthe semiconductor device on a mount board by inserting leads of thesemiconductor device into through-holes formed in the mount board.

Besides, various modifications may be made within the scope of theappended claims. It should be understood that the embodiments describedabove are merely illustrative of the technical principles of the presentinvention but not limitative of the invention. The spirit and scope ofthe present invention are to be limited only by the appended claims.

1. An interposer to be provided together with a semiconductor chip in asemiconductor device and, when the semiconductor device is mounted on amount board, disposed between the semiconductor chip and the mountboard, the interposer comprising: an insulative substrate of aninsulative resin; an island provided on one surface of the insulativesubstrate to be bonded to a rear surface of the semiconductor chip via abonding agent; a thermal pad provided on the other surface of theinsulative substrate opposite from the one surface in generally opposedrelation to the island with the intervention of the insulativesubstrate, the thermal pad having substantially the same size and planshape as those of the island; and a thermal via extending through theinsulative substrate from the one surface to the other surface toconnect the island to the thermal pad in a thermally conductive manner.2. The interposer according to claim 1, further comprising: internalterminals provided on the one surface of the insulative substrate forelectrical connection to the semiconductor chip; external terminalsprovided on the other surface of the insulative substrate for electricalconnection to lands on the mount board; and inter-terminal connectionvias extending through the insulative substrate from the one surface tothe other surface to respectively electrically connect the internalterminals to the external terminals.
 3. The interposer according toclaim 2, further comprising a thermal bump provided on the thermal padand adapted to abut against the mount board with the semiconductordevice mounted on the mount board.
 4. The interposer according to claim3, wherein the island, the thermal pad, the thermal via and the thermalbump are electrically conductive, wherein the bonding agent is composedof a metal material, wherein the thermal bump is adapted to abut againsta ground terminal on the mount board with the semiconductor devicemounted on the mount board. wherein the thermal pad has substantiallythe same thickness as that of the island.
 5. The interposer according toclaim 4, wherein the bonding agent is a high melting point solder.
 6. Asemiconductor device comprising: a semiconductor chip; an insulativesubstrate of an insulative resin; an island provided on one surface ofthe insulative substrate and bonded to a rear surface of thesemiconductor chip via a bonding agent; a thermal pad provided on theother surface of the insulative substrate opposite from the one surfacein generally opposed relation to the island with the intervention of theinsulative substrate, the thermal pad having substantially the same sizeand plan shape as those of the island; and a thermal via extendingthrough the insulative substrate from the one surface to the othersurface to connect the island to the thermal pad in a thermallyconductive manner.
 7. The semiconductor device according to claim 6,further comprising: internal terminals provided on the one surface ofthe insulative substrate and electrically connected to the semiconductorchip; external terminals provided on the other surface of the insulativesubstrate for electrical connection to lands on a mount board on whichthe semiconductor device is mounted; and inter-terminal connection viasextending through the insulative substrate from the one surface to theother surface to respectively electrically connect the internalterminals to the external terminals.
 8. The semiconductor deviceaccording to claim 7, further comprising a thermal bump provided on thethermal pad and adapted to abut against the mount board with thesemiconductor device mounted on the mount board.
 9. The semiconductordevice according to claim 8, wherein the island, the thermal pad, thethermal via and the thermal bump are electrically conductive, whereinthe bonding agent is composed of a metal material, wherein the thermalbump is adapted to abut against a ground terminal on the mount boardwith the semiconductor device mounted on the mount board, wherein thethermal pad has substantially the same thickness as that of the island.10. The semiconductor device according to claim 9, wherein the bondingagent is a high melting point solder.